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Tier-1 brand and metro Bangalore location increase applicant density despite niche VLSI specialization.
Highly specialized VLSI verification skills limit cross-industry transferability.
Explicit 8-12 years, mandatory verification tools and VLSI expertise make filters highly strict.
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Lead verification efforts for complex IP blocks, sub-systems, and SoC designs to ensure functional verification closure.
Develop and execute comprehensive verification strategies, test plans, and verification infrastructure including reusable components and assertions using System Verilog and UVM.
Mentor junior engineers and collaborate across design, validation, and cross-functional teams to drive design quality and silicon success.
8 to 12 years of relevant experience in VLSI design verification.
Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering; Master's degree preferred.
Advanced proficiency in C, Verilog, System Verilog, and UVM; experience with verification tools like Xcellium, Verdi, and JasperGold formal verification tools.
Proven experience across verification lifecycle including planning, testbench and test case development, regression management, coverage analysis, debugging, and sign-off.
Demonstrated leadership in technical projects with ability to manage stakeholder relationships effectively.
Experience with NAND flash memory protocols and memory design verification is preferred.
Experienced in mentoring junior engineers and contributing to process improvements with exposure to AI/ML/Automation initiatives in verification environments.