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Tier-1 brand and Bangalore metro increase competition despite niche ASIC verification specialization.
Highly domain-specific ASIC/SoC verification expertise limits transferability across industries.
Explicit 13+ years and mandatory specialized ASIC verification skills create highly restrictive shortlisting criteria.
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Own end-to-end verification flows for one or more SoC subsystems including planning, execution, and closure.
Define verification strategies and develop UVM/SystemVerilog environments to validate complex SoC hardware and ensure coverage goals are met.
Mentor junior and mid-level engineers, lead verification methodology improvements, and collaborate across architecture, design, and validation teams for system-level issue resolution.
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
At least 13 years of experience in ASIC/SoC verification.
Strong proficiency in C, SystemVerilog UVM, coverage-driven verification, and protocol knowledge including PCIe, AXI, AHB, APB, LPDDR, I2C, I3C, SPI.
Experience with gate-level simulation (including SDF annotation), power-aware verification (UPF/CPF), and scripting languages like Python, Perl, TCL.
Experienced in developing and scaling reusable verification methodologies and regression infrastructures for SoC-level verification.
Strong debugging skills across digital logic, firmware, timing, and DFT domains, with ability to verify complex datapath flows of storage controllers.
Demonstrated ability to lead collaboration across cross-functional teams including RTL design, validation, firmware, and physical design to deliver robust verification outcomes.