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Tier-1 employer and Bangalore location increase competition, but niche ASIC validation reduces broad applicant pool.
ASIC/SoC validation expertise is highly specialized, limiting transferability across industries.
Explicit 9–13 years plus protocol, emulation and firmware requirements create stringent shortlisting filters.
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Own end-to-end validation flows for one or more SoC subsystems including planning, execution, and closure.
Lead and mentor validation engineers, reviewing their test plans and debugging approaches to ensure coverage and closure targets.
Define and drive SoC-level validation strategies and sign-off criteria (functional, performance, power, stress, PVT) across multiple teams, spanning pre- and post-silicon validation including complex datapath and protocol scenarios.
9 to 13 years of experience in SoC pre- and post-silicon validation and bring-up.
Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
Validation experience with DDR and PCIe protocols, including at pre- and post-silicon stages.
Proficiency in embedded programming (C), hardware/software co-validation, SystemVerilog and UVM concepts, and experience in SoC validation infrastructure development.
Experienced in leading and mentoring teams in complex SoC validation environments with accountability for validation strategies and sign-off.
Strong cross-domain debugging skills across digital, firmware, timing, low-power, and DFT using industry-standard tools and methods.
Proficient in both firmware/HAL development and use of emulation platforms (e.g. Palladium) to accelerate SoC validation, with ability to work collaboratively across design, verification, and product engineering teams.