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Tier-1 employer and remote hiring increase applicant density, balanced by seniority and niche EDA specialization.
Highly specialized semiconductor EDA tooling work yields low cross-industry transferability and high domain bias.
Explicit 9+ years and specialized CAD/EDA, Python, SystemVerilog, and tooling requirements make filters strict.
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Lead design and implementation of a comprehensive automation tool for SoC chassis configurations including RTL, register definitions, and verification collateral generation.
Collaborate closely with architecture, RTL design, verification, and SoC integration teams to encode architectural rules and ensure output quality and correctness.
Mentor junior engineers and drive best practices in software design, testing, and maintenance while managing delivery schedules and priorities across multiple SoC programs.
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
9+ years of experience in CAD/EDA tooling, design automation, or semiconductor development.
Strong proficiency in Python or similar languages and understanding of SoC digital design concepts such as RTL hierarchy and parameterized IP.
Experience with schema design (JSON/YAML), SystemVerilog for validation, templating/code generation frameworks, and software engineering best practices including Git and CI/CD.
Experienced in developing scalable, maintainable software systems in semiconductor or EDA environments, especially with automation for SoC subsystems.
Familiarity with interconnect protocols (AXI, CHI, PCIe, UCIe), IP packaging/integration standards like IP-XACT, and graph algorithms relevant to topology and routing.
Capable of translating architecture specifications into robust software solutions, collaborating cross-functionally and balancing multiple delivery schedules.