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Tier-1 brand and Bangalore location increase applicant density, but niche hardware verification skill narrows candidate pool.
Specialized ASIC verification skills (SystemVerilog, UVM, PCIe/CXL) limit cross-industry transferability.
Highly specific mandatory skills and RTL/UVM experience with explicit years requirement enforce strict shortlisting.
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Develop and maintain UVM-based verification environments and execute verification plans for high-speed interconnect protocols like PCIe, CXL, and AXI.
Perform block-level and top-level verification including functional coverage, assertion-based verification, and regression testing to ensure design correctness and coverage closure.
Collaborate closely with RTL designers, architects, and validation teams; mentor junior engineers; and contribute to methodology improvements and verification closure through coverage convergence.
Bachelor’s degree with 4+ years, Master’s with 3+ years, or PhD with 2+ years of Hardware Engineering or related experience.
Strong proficiency in SystemVerilog, UVM, and verification methodologies.
Deep understanding of PCIe (Gen3/Gen4/Gen5/Gen6), CXL (1.1/2.0/3.0), AXI/CHI protocols and SMMU/Coresight architecture.
Experience using Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols, and skills in assertion-based verification and scripting (Perl/Python/Tcl).
Experienced ASIC/Subsystem/SoC verification engineer with 8–12+ years experience handling complex high-speed interconnect protocols.
Strong background in coverage-driven, assertion-based verification and debugging RTL and gate-level simulations.
Capable of collaborating across design, architecture, and validation teams with a focus on verification closure, methodology enhancement, and mentoring junior engineers.