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Tier-1 employer and Bangalore location increase applicant density despite senior niche EDA requirements.
Strong ASIC/EDA specialization limits transferability across industries.
Explicit 12–15 years requirement plus mandatory EDA tools and advanced-node experience.
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Own interfacing with customers to gather and scope digital reference flow requirements for synthesis, floorplanning, clock tree synthesis, power planning, place and route, timing closure, and sign-off.
Develop baseline digital implementation flows and implement test cases for process certification and validation, supporting Tempus and Voltus sign-off.
Create documentation explaining reference flow steps and commands, and contribute towards PPA (power, performance, area) optimization.
Bachelor's degree with 12-15 years of design/EDA experience or Master's degree with 10+ years experience (Master's preferred).
Mandatory expertise in Digital Design Flows, Static Timing Analysis, and EMIR.
Experience with ASIC digital implementation flows and EDA tools (Genus, Innovus, Tempus, Voltus) including advanced FinFet nodes (7nm and below).
Proficiency in Unix, Shell scripting, Perl and TCL scripting languages with strong customer-facing communication skills.
Experienced in leading customer-facing digital implementation flow projects with deep domain expertise in ASIC and advanced process technologies.
Technically proficient operator of EDA tools setup, debugging, and digital design flow validation in a complex engineering environment.
Able to translate deep technical knowledge into clear documentation and optimized PPA outcomes while collaborating with customers and engineering teams.