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Tier-1 brand and Bangalore metro increase competition, but niche SoC DV skills moderate applicant pool.
Highly specialized SoC verification expertise limits transferability across industries.
Explicit 5+ years and mandatory deep DV, UVM/SystemVerilog, formal verification, and scripting requirements drive high strictness.
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Define and execute end-to-end verification strategy for multiple testchips from planning through signoff, ensuring on-time delivery of quality test collateral.
Lead development of reusable verification environments, tools, and complex testplans including testbenches, checkers, VIPs, and behavioural models.
Collaborate cross-functionally to unblock issues, drive functional signoffs, coverage closure, and mentor junior engineers while adopting emerging AI-driven verification methodologies.
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
5+ years of relevant experience in design verification with strong SoC and subsystem-level expertise.
Proficient in SystemVerilog/UVM, C/C++, Python, simulation and formal verification methodologies (UVM, SVA, ABV, co-simulation), and low-power verification techniques.
Working familiarity with RTL and physical design constraints, with experience in debug, trace, clock, and power management verification.
Experienced in leading verification strategies for complex SoC IP blocks with measurable quality and schedule impact.
Operates effectively across multiple disciplines including architecture, design, and physical design to unblock cross-team dependencies.
Comfortable leveraging AI-assisted workflows and continuously adopting emerging verification technologies and methodologies.