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Intel brand, metro Bangalore, mid-level role but specialized mixed-signal skills reduce broad competition.
Highly specialized hardware/IP verification skills and DDR PHY domain make cross-industry transfers difficult.
Explicit 5–10 years plus mandatory SystemVerilog/UVM, DDRPHY and simulation tool experience enforces strict filters.
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Own the complete functional verification flow for DDR PHY IP ensuring design meets specification across IP, subsystem, and SoC levels.
Develop and execute validation strategies including test plan creation, testbench architecture, test automation, and debugging in pre-silicon environments.
Collaborate with cross-functional teams (digital, analog, RTL, physical design) to improve verification methodology and infrastructure.
5-10 years of experience in Design Verification specializing in System Verilog and OVM/UVM environments.
Proficient in validation flow from testbench architecture, test plan creation to verification closure including simulations (VCS NLP/non-NLP), coverage, and waveform debug.
BS or MS degree in a relevant field.
Work Location: Bangalore, India; eligible for hybrid work model.
Experienced in DDR PHY validation with understanding of Design For Testability (DFx) features.
Skilled in scripting using Python or Perl for automation within verification flows.
Capable of operating effectively in a dynamic, multi-geography team environment with strong debugging and problem-solving skills.