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Strong Tier-1 brand and remote role increase competition, while niche EDA seniority reduces applicant pool.
Specialized semiconductor EDA tooling demands domain-specific experience, limiting cross-industry transferability.
Explicit 9+ years, mandatory CAD/EDA tooling experience and technical skills make filters strict.
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Lead design and implementation of a new automated tool for SoC chassis parameterization, RTL generation, and verification collateral creation.
Collaborate directly with architecture, RTL design, verification, and SoC integration teams to ensure tool accuracy and meet multiple internal customer requirements.
Drive end-to-end delivery and ongoing maintenance of the automation framework while mentoring junior engineers and establishing best practices.
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
Minimum 9 years experience in CAD/EDA tooling, design automation, or semiconductor development.
Strong proficiency in Python or similar language with experience building scalable and maintainable software systems.
Working knowledge of SystemVerilog and experience with structured schemas like JSON/YAML, and code generation frameworks.
Experienced in semiconductor SoC digital design concepts, including RTL hierarchy, synthesis, and parameterized IP.
Able to translate architecture specifications into robust automated software implementations affecting multiple SoC programs.
Proven ability to lead cross-disciplinary collaboration and deliver scalable tooling impacting SoC chassis automation and integration quality.