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Tier-1 employer and metro location increase applicant competition.
Highly specialized ASIC verification skills limit transferability across industries.
Explicit 5+ years requirement and mandatory SystemVerilog/UVM and tool experience raise strictness.
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Lead verification of high-speed mixed-signal IP designs including PLL, DAC, ADC, USB, PCIe, MIPI, and other interfaces targeting 5G, AI/ML, compute, IoT, and automotive applications.
Define and execute pre-silicon and post-silicon test plans, architect and develop testbenches using SystemVerilog/UVM and advanced verification methodologies including low power, formal verification, and gate level simulation.
Collaborate closely with digital, analog, subsystem, and SoC teams for PHY-level verification, integration, and post-silicon validation activities.
Master’s or Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
5+ years of ASIC design verification, pre-silicon verification, or related experience.
Proficiency with HVL methodologies such as SystemVerilog/UVM and ASIC verification tools (VCS, Xcelium/NCsim, Modelsim/Questa, VCFormal, Jaspergold).
Work Experience Required: Minimum 5 years in ASIC design verification or related roles.
Experienced in complex mixed-signal IP verification including USB, PCIe, CXL, PLLs, data converters, sensors, or associated technologies.
Skilled in advanced verification techniques like low power design verification, formal methods, and gate level simulation.
Proficient in scripting languages such as Python or Perl, comfortable working in multi-disciplinary teams integrating IP with SoC and subsystem designs.