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Tier‑1 employer and Bangalore location raise competition, mitigated by senior, niche EDA specialization.
Role requires deep EDA and ASIC implementation expertise, limiting cross-industry transferability.
Explicit 12–15 years, advanced-node expertise, specific EDA tools and scripting make filters highly stringent.
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Interface with customers to gather and clarify digital reference flow requirements for synthesis, floorplanning, clock tree synthesis, power planning, place and route, timing closure, and sign-off.
Develop baseline digital implementation flows and create testcases for process certification and validation using EDA tools such as Tempus and Voltus.
Document reference flow methodologies and optimize performance, power, and area (PPA) for digital design flows.
Bachelor’s degree with 12-15 years design/EDA experience or Master’s degree with at least 10 years (Master’s preferred).
Strong knowledge of Digital Design Flows, Static Timing Analysis, and EMIR.
Prior experience with ASIC digital implementation flows and EDA tools, including advanced FinFET nodes (7nm and below).
Proficient in Unix, Shell scripting, Perl, and TCL; familiar with EDA tools such as Genus, Innovus, Tempus, and Voltus.
Experienced in customer-facing roles requiring gathering technical requirements for digital implementation flows.
Skilled in digital ASIC design and verification with a focus on advanced process nodes, including FinFET and preferably GAA technologies.
Hands-on operational expert with EDA tool setup, debugging, and test case implementation in digital design flows.