Back
Tier-1 brand and metro location increase competition despite niche DFT specialization.
Highly domain-specific semiconductor DFT skills limit transferability across industries.
Explicit 7-12 years DFT experience and specialized technical requirements make screening highly restrictive.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own and execute Design for Test (DFT) insertion flows including scan chain, compression scan, LBIST, and memory BIST to meet test coverage goals.
Perform ATPG, debug and analyze test failures, and verify ATPG testbenches ensuring design test coverage and simulation accuracy.
Collaborate across architecture, design, and customer teams to deliver DFT tasks independently within fast-paced SoC/ASIC digital design projects.
7-12 years of professional experience in SoC/ASIC Digital Design focusing on Design for Test (DFT).
Proficient in DFT insertion flows including scan chain, compression scan insertion, LBIST, MBIST, and ATPG.
Working knowledge of JTAG standards (1149.1/6), IEEE1500 and IEEE1687.
Experience with Cadence tools and flows is highly desirable; knowledge of timing analysis and equivalency checks is a plus.
Experienced in independently handling complete DFT tasks within complex SoC/ASIC projects with strong problem-solving aptitude.
Comfortable working in collaborative cross-functional teams involving architecture, design, and external/internal customers.
Disciplined and methodical with demonstrated ability to debug test failures and optimize fault coverage effectively.