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Tier-1 employer and Bangalore location increase competition, but niche DFT specialization reduces applicant pool.
Specialized ASIC/DFT expertise limits cross-industry transferability.
Explicit 7–12 years requirement and specialized DFT/ATPG technical mandates tighten shortlisting.
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Own full lifecycle of Design for Test (DFT) insertion flows including scan chain, compression scan, LBIST, and MBIST for SoC/ASIC Digital Designs.
Lead debugging and analysis of test failures to improve fault coverage and verify ATPG testbenches.
Collaborate across Architecture, Design, and Internal/External stakeholders to deliver DFT tasks independently in a fast-paced environment.
7-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT).
Intimate knowledge of DFT insertion flows, including scan chain insertion, compression scan, LBIST, and MBIST.
Expertise in Automatic Test Pattern Generation (ATPG) and failure debugging.
Familiarity with JTAG 1149.1/6, IEEE1500, IEEE1687; knowledge of timing analysis and equivalency checks is a plus.
Experienced in independently completing complex DFT tasks and debugging in silicon design environments.
Comfortable collaborating with cross-functional teams including Architecture, Design, and Customers.
Operates methodically with strong problem-solving skills and discipline in a fast-paced project setting.