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Tier-1 brand and metro location but highly specialized SoC/VLSI senior role reduces broad applicant density.
Highly domain-specific ASIC/SoC and EDA expertise substantially limits cross-industry transferability.
Explicit 10–15 years VLSI requirement plus mandatory ASIC/EDA/DFT expertise makes filters highly stringent.
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Own full lifecycle program management of semiconductor SoC projects from architecture specification to tape-out and silicon validation.
Align and coordinate cross-functional engineering teams including RTL, Physical Design, Verification, and DFT to meet project timelines, budgets, and quality standards.
Proactively manage risks, resource constraints, and track milestones while providing regular stakeholder communication and project status updates.
10-15 years of experience in VLSI engineering with project management experience.
Bachelor's or Master's degree in Electrical Engineering, Electronics, or related field.
Deep technical knowledge of VLSI design flow, ASIC/SoC design, and EDA tools.
Experience with project management software and methodologies.
Experienced program manager with strong technical background in digital, analog, mixed-signal design, DFT, and FPGA.
Proven ability to lead and synchronize cross-functional teams (RTL design, verification, physical design, DFT) in complex semiconductor projects.
Skilled in risk identification, mitigation planning, and communication to manage stakeholder expectations effectively.