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Niche hardware verification skills but metro location and mid-level seniority make competition moderate.
Specialized hardware verification and VIP/AIP expertise limit transferability across industries.
Explicit mandatory SystemVerilog/UVM experience and a 3+ years expectation make filters strict.
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Develop, maintain, and scale SiFive's Verification Platform including VIPs, AIPs, and testbench components using System Verilog, UVM, and related technologies.
Create Verification Platform libraries in Scala with Chisel for verification intent expression, including test harnesses, stimulus, and scoreboards.
Develop and execute test plans for testbench components quality assurance and provide education on Verification Platform best practices to verification teams.
3+ years Design Verification experience with System Verilog and UVM.
Experience designing and verifying VIPs, AIPs, and testbench components.
BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Legal authorization to work in India and pass background and reference checks.
Strong background in Design Verification engineering coupled with solid software engineering skills.
Experience working with or willingness to work in a Chisel and Scala-based verification environment.
Familiarity with DevOps practices, EDA tools and flows for Design Verification, and CI/CD pipelines.