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Tier-1 employer, mid-level experience, metro location, but niche EDA specialization reduces broad applicant competition.
Highly specialized EDA and timing signoff expertise limits transferability across industries.
Mandatory 3–4 years and specialized EDA, timing signoff, and scripting skills enforce strict shortlisting.
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Accountable for validating, improving, and regressing Cadence’s Tempus signoff ECO product to ensure high-quality solutions.
Collaborate with R&D professionals, senior product engineers, and product release teams to define product specifications and enhance product quality for complex customer needs.
Develop product flows and test methodologies, automate processes to improve overall system efficiency and performance.
MS in Electrical/Electronics/Computer Engineering with 3+ years experience OR BE/BTech in Electrical/Computer/Electronics Engineering with 4+ years relevant experience.
In-depth knowledge of Static Timing Analysis, Signal Integrity, Delay calculation, timing constraints, report_timing commands, timing analysis, Verilog, and debugging.
Experience with Timing and power closure using ECO (automated and manual) and familiarity with front-end/back-end design flows.
Skills with Physical Design Implementation platforms (like Innovus) and scripting languages such as Perl, TCL, Python, or C Shell for automation.
Experienced with timing signoff solutions at block or full chip level, preferably in complex ECO environments.
Operates effectively in cross-functional and cross-geographic teams, demonstrating strong communication and collaboration skills.
Proactive in identifying automation opportunities and developing test methodologies to enhance product quality and efficiency.