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Tier-1 employer but senior niche ASIC validation skillset limits applicant volume.
Highly domain-specific ASIC/SoC validation skills not easily transferable outside semiconductor industry.
Strict 8+ years and mandatory HAPS/Vivado/Verilog/VCS and scripting requirements.
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Own complete SoC deployment on Pre Silicon platforms such as HAPS including prototyping, emulation, and FPGA implementation.
Develop and execute PCIe/LPDDR/ONFI validation plans in collaboration with Design/SOC C/FW/AE teams.
Perform hands-on FPGA debug and Verilog RTL coding using Xilinx Ultrascale FPGA, Vivado, Protocompiler, and Chipscope flow.
Minimum 8 years of experience in processor-based SoC and hands-on HAPS implementation.
Bachelor’s or Master’s degree in Engineering or equivalent experience.
Strong proficiency in Xilinx FPGA flows including Vivado, Protocompiler, and HAPS80 (HAPS100 preferred).
Proven skills in Verilog coding and scripting languages (Python, Perl, TCL).
Experienced in cross-functional collaboration with design, firmware, and AE teams to coordinate SoC validation and debug.
Skilled in root cause analysis across hardware and RTL layers with strong FPGA debug expertise.
Comfortable working with international teams for PCIe/LP bring-up and debugging tasks.