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Strong employer brand and metro location increase interest, but niche mixed-signal verification skills limit applicants.
Mixed-signal VLSI verification requires specialized hardware and EDA skills, limiting cross-industry transferability.
Explicit 4–12 year band plus mandatory SystemVerilog/UVM, EDA tool and scripting expertise increases screening rigor.
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Lead functional verification of mixed signal logic components and analog behavioral models to meet design specifications.
Develop and execute verification plans, test benches, and simulation models ensuring comprehensive coverage of mixed signal microarchitecture specs.
Collaborate closely with architects, RTL developers, and physical design teams to debug and optimize presilicon designs.
Bachelor's or Master's degree in Electronics, VLSI Engineering, or related field.
4-12 years of relevant experience in mixed signal design verification.
Proficiency in System Verilog, UVM, Verilog, and EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa.
Strong scripting skills in Python, Perl, or Tcl; Knowledge of protocols like JTAG/IJTAG/CRI/APB and multi-clock domain mixed signal designs.
Experience validating mixed signal IPs with expertise in constraint-random test generation and detailed root cause debugging.
Ability to integrate verification infrastructure improvements supporting advanced microarchitecture and low-power design techniques.
Comfortable operating within multi-disciplinary teams involving analog, digital, and physical design functions in a dynamic, on-site environment.