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Niche ASIC/SoC verification role requires specialized UVM/SystemVerilog skills, limiting applicant pool.
Highly domain-specific ASIC/SoC verification skills limit cross-industry transferability.
Requires specialized verification skills and EDA tool experience, making filters strict.
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Develop and execute advanced verification plans for complex ASIC/SoC/IP designs ensuring functional correctness with UVM methodology.
Build and maintain scalable SystemVerilog/UVM verification environments including reusable testbenches and agents.
Debug RTL, testbench, and simulation issues; automate regression flows to improve verification productivity.
Proficiency in SystemVerilog and hands-on experience with UVM (Universal Verification Methodology).
Familiarity with functional coverage, assertions (SVA), constrained random verification, and EDA tools (e.g., VCS, Verdi).
B.Tech/M.Tech in Electronics, Electrical, Computer Engineering or equivalent.
Work Experience Required: Not explicitly mentioned in the JD.
Experience in complex SoC/IP design verification with strong focus on verification methodologies and automation.
Ability to collaborate cross-functionally with design, architecture, and physical design teams to deliver silicon first-time-right.
Experience with protocols such as AXI, AHB, APB, PCIe and scripting skills (Python/Perl/Shell) for verification environment automation.