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Niche hardware verification skills reduce applicants, but metro location and mid-level role keep competition moderate.
Hardware verification skills are highly domain-specific and transfer poorly outside semiconductor and chip-design industries.
Explicit 3+ years and mandatory SystemVerilog/UVM and VIP experience enforce strict candidate filters.
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Develop and maintain the Verification Platform including VIPs, AIPs, and testbench components used across SiFive.
Architect and enhance testbench libraries in Scala/Chisel and SystemVerilog/UVM enabling scalable design verification infrastructure.
Collaborate with Design Verification and validation teams to integrate and ensure high-quality reusable testbench components and educate on best practices.
3+ years of Design Verification experience involving SystemVerilog and UVM.
Experience designing and verifying VIPs, AIPs, and testbench components.
Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Work Authorization: Must have the legal right to work in India; successful background and reference checks required.
Strong expertise in Design Verification with hands-on experience in reusable verification component development.
Comfortable with both hardware verification languages (SystemVerilog/UVM) and modern software engineering practices, including Scala and Chisel.
Experience or interest in EDA tools, DevOps/CI-CD processes to support scalable testbench infrastructure.