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Tier-1 brand and Bengaluru metro increase competition, but niche PCIe/firmware skills limit applicant pool.
Specialized firmware and PCIe validation experience is highly domain-specific and not easily transferable.
Explicit 6–8 years, mandatory PCIe/firmware expertise, and pre/post‑silicon lab skills create strict filters.
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Own design and development of Python-based white box and gray box tests for verifying SSD firmware features, especially PCIe protocol features.
Define and execute comprehensive firmware verification and validation strategies for PCIe front-end subsystems, including MMIO, DMA, BARs, resets, interrupts, and error handling across pre-silicon and post-silicon platforms.
Lead failure analysis, test integration in automation frameworks, compliance validation, and collaborate cross-functionally to ensure firmware specs and tests meet product requirements.
Bachelor's or Master's degree in CSE, ECE, EEE, IS, or related field.
6-8 years of experience in firmware verification or system-level testing including PCIe Gen5/Gen6 protocol testing.
Strong knowledge of PCIe Gen3/Gen4/Gen5 (Gen6 preferred) protocols including LTSSM, TLP/DLLP, flow control, and error handling.
Proficient in Python scripting for test development; experienced with protocol analyzers (e.g., Teledyne LeCroy, Keysight) and familiar with pre-silicon (simulation/emulation) and post-silicon lab validation environments.
Experienced in high-performance storage or compute SoCs with strong ASIC front-end architecture knowledge related to PCIe, MMIO, BARs, and DMA.
Demonstrated leadership in test strategy definition, technical reviews, mentoring, and driving validation readiness across multiple platforms.
Skilled in debugging firmware-hardware interactions, failure analysis, and integrating tests into scalable automation frameworks using scripting and CI tools.