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Tier-1 brand, mid-level experience and metro location, but specialized EDA timing skills reduce broad applicant density.
Strong EDA, static timing and physical-design focus makes cross-industry transfer difficult.
Explicit 4+ years plus domain-specific static timing, ECO, Innovus and scripting requirements increase shortlisting rigidity.
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Validate, improve, and regress functionality of the Tempus signoff ECO solution to ensure high product quality.
Collaborate with R&D, senior product engineers, and product release teams to define specifications and enhance product quality addressing complex customer and market needs.
Develop and automate product flows and test methodologies to improve quality, performance, and overall system efficiency.
MS in Electrical/Electronics/Computer Engineering with 3+ years experience or BE/BTech in Electrical/Computer/Electronics Engineering with 4+ years relevant experience.
In-depth knowledge of Static Timing Analysis, Signal Integrity, Delay calculation, timing constraints, report_timing commands, timing analysis, Verilog and debug skills.
Experience in timing and power closure with ECO (both automated and manual) and physical design implementation tools like Innovus or similar.
Proficiency in scripting languages such as Perl, TCL, Python or C Shell for automation purposes.
Experienced in timing signoff solutions at block or full chip level, ideally with knowledge of QA practices and methodologies.
Able to identify complex problems, develop and evaluate solutions independently, and execute automation requirements.
Strong communication skills enabling effective cross-geographic collaboration with customer peers and management; able to work across functions and geographies efficiently.