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Strong employer brand but niche SystemVerilog/UVM skills limit applicant pool.
Hardware/IP verification skills are highly domain-specific and not easily transferable across industries.
Explicit years and mandatory verification methodologies and languages make shortlisting stringent.
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Lead IP-level verification of GPU ASICs focusing on graphics and compute features.
Develop and execute test plans, tests, and verification infrastructure using UVM methodology ensuring functional and code coverage of RTL.
Collaborate with hardware architects, designers, and verification teams to validate design, architecture, and micro-architecture decisions.
B.Tech. or M.Tech. degree.
2+ years of relevant experience in verification and test planning at Unit level.
Proficiency with Verilog, C++, OOP concepts, and functional coverage-based constrained random verification environments.
Familiarity with SystemVerilog or similar HVL, and verification methodologies like UVM or VMM.
Experience with GPU or 3D graphics processing or processor verification.
Strong understanding of computer architecture and advanced verification tools for simulation and debug.
Skills in C/C++, scripting (Perl, Python), and strong debugging capabilities for effective problem resolution.