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Tier-1 employer and Bangalore metro raise applicant density, but niche ASIC verification moderates competition.
ASIC/SystemVerilog verification skills are industry-specific, limiting cross-industry transferability.
Explicit degree-year minima and specialized verification technologies create stringent screening filters.
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Develop and maintain UVM-based verification environments for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.
Perform block-level and top-level verification encompassing functional coverage, assertion-based verification, and regression testing to ensure design correctness and coverage closure.
Collaborate with RTL designers, architects, and validation teams; mentor junior engineers; and contribute to verification methodology improvements and debugging at RTL and gate-level simulations.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering or related field with 6+ years of related work experience; OR Master's degree with 5+ years experience; OR PhD with 4+ years experience.
Strong proficiency in System Verilog, UVM, and verification methodologies.
Deep understanding of PCIe Gen3 to Gen6, CXL 1.1 to 3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
Experience with assertion-based verification (SVA), coverage-driven testing, scripting in Python/Perl/Tcl, and use of Synopsys/Mentor VIPs for protocol compliance.
Senior-level ASIC/Subsystem/SoC verification engineer with 8–12+ years of experience focusing on high-speed interconnect protocols and verification closure.
Expert in UVM-based verification environments and knowledgeable in protocol compliance using third-party VIPs.
Experienced collaborator with cross-functional teams, capable of leading verification strategy development and mentoring junior engineers.