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Strong Tier-1 employer and Bangalore location increase competition, but senior niche SoC verification reduces applicant density.
Highly specialized pre-silicon SoC verification skills have limited transferability across industries.
Explicit 8–15 years and mandatory SystemVerilog/UVM SoC verification make shortlisting highly strict.
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Ensure functional correctness and quality of SoC designs before silicon tape-out via simulation, emulation, and advanced verification methodologies.
Develop and maintain System Verilog/UVM-based testbenches and verification environments including constrained-random and directed test scenarios.
Lead debugging, root-cause analysis, coverage closure, and collaboration with architecture, RTL design, post silicon, and validation teams while mentoring junior engineers.
8 to 15 years of experience in SoC/subsystem/IP level pre-silicon verification.
Bachelor’s or Master’s degree in Electronics, Computer Science, or related field (BE/B.Tech/M.Tech in ECE or Computer Science).
Proficiency in System Verilog and UVM based verification methodologies.
Location: Bangalore, India; Eligible for hybrid work model.
Experienced in leading verification activities and mentoring junior team members to deliver high-quality projects.
Strong expertise in functional verification including simulation, emulation, constrained-random testing, and coverage-driven verification.
Skilled at debugging RTL and testbench failures with a focus on improving verification methodologies and automation workflows.