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Tier-1 employer, Bangalore location and mid-level experience increase competition, but niche SystemVerilog/UVM skills moderate it.
Highly domain-specific hardware verification skills reduce cross-industry transferability.
Mandatory degree, explicit years and specialized SystemVerilog/UVM and protocol expertise make filters stringent.
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Develop and execute detailed verification plans for IP logic ensuring adherence to microarchitecture specifications.
Create and maintain test benches and verification environments using OVM and UVM methodologies.
Collaborate with architects, RTL, and physical design teams to validate complex features, analyze power and timing impacts, and improve verification strategies.
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
4+ years (Bachelor's) or 3+ years (Master's) experience in IP-level design verification.
Proficiency in hardware simulation, SystemVerilog, and verification methodologies such as OVM and UVM.
Working knowledge of interconnect and bus protocols (AMBA AXI/ACE/CHI, PCIe, or CXL) and cache coherency concepts.
Experienced in developing and executing IP test plans and creating verification environments for complex microarchitectures.
Skilled at root cause analysis of failing tests and driving corrective design measures.
Able to collaborate effectively across multiple teams and lead technical reviews to enhance verification frameworks.