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Tier-1 employer, metro location, and mid-level range increase competition despite niche DDR specialization.
Highly specialized DDR driver and embedded skills limit cross-industry transferability.
Explicit years plus mandatory niche DDR and low-level driver skills enforce strict filtering.
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Own debugging and development of DDR initialization and runtime driver sequences for LP4x/LP5x technologies.
Drive multiple DDR-related programs by collaborating cross-functionally with teams focused on performance, PHY, and controller design to resolve system-level memory issues.
Analyze system data, identify patterns, triage DDR issues, and enhance test cases to ensure DDR stability, power efficiency, and performance goals are met.
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field with 3+ years of software engineering experience; or Master's with 2+ years; or PhD with 1+ year experience.
2+ years academic or work experience programming in C, C++, Java, or Python.
Relevant work experience in DDR technology involving memory controllers, PHY, DRAMs, firmware, software driver development, platform driver development, or board bring-up.
Experience with embedded systems, SOC architecture, RTOS, CPU architecture, JTAG, and BSP driver-level development and debugging.
Experienced in system-level test methodologies and validations focused on DDR stability and memory corruption issues.
Able to independently manage multiple chipsets and drive the DDR software system to commercial launch readiness.
Strong analytical skills with ability to collaborate across hardware and software teams to solve complex DDR system problems and improve test coverage.