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Tier-1 employer and metro location increase applicant density despite niche senior hardware verification requirements.
Requires deep SoC verification and DV CAD expertise, limiting cross-industry transferability.
Mandatory 12+ years and specialized DV/CAD skills make screening highly selective.
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Lead development and evolution of DV methodologies and UVM-based testbench architectures across IP and SoC verification.
Architect and deploy Agentic AI workflows and GenAI tools for automation in Design Verification (DV) including testplan generation, code generation, and debug.
Develop and maintain CAD tools and automation scripts, support verification and formal tools, and drive emulation/prototyping enablement for pre-silicon validation.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years, or Master's degree with 5+ years, or PhD with 4+ years of relevant Hardware Engineering experience.
12+ years in Design Verification / Verification CAD with deep expertise in SystemVerilog-UVM testbench development, constrained random verification, functional coverage, and SVA scripting & automation.
Proficiency in Python, Perl, TCL, Makefile-based flows, and experience with verification tools like VCS, Xcelium, Verdi/DVE, and emulation platforms like Palladium/Veloce.
Experience or strong interest in Agentic/GenAI technologies for DV automation and methodology including verification planning and coverage-driven verification.
Senior level engineer with extensive hands-on and leadership experience in design verification CAD and methodology development.
Experience collaborating cross-functionally with DV teams, IP teams, and AI/GenAI platform groups to integrate emerging technologies in verification workflows.
Strong technical mentor and driver of efficiency KPIs such as regression turnaround time, coverage closure, and bug escape metrics in complex SoC environments.