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Tier-1 employer and metro location increase competition, but DDR firmware specialization reduces applicant pool.
Highly specialized DDR, SOC and firmware expertise is industry-specific and not easily transferable across domains.
Explicit years plus mandatory low-level firmware, driver and SOC skills create strict screening filters.
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Own and drive development and debugging of DDR system software drivers and firmware, focusing on DDR initialization and runtime sequences for LP4x/LP5x technologies.
Collaborate with multiple teams (performance, PHY, controller design) to triage and resolve system-level DDR issues such as memory corruption, bit flips, CPU hangs, and run system-level validation tests.
Analyze large datasets to recognize patterns and contribute across product development stages from development to commercial launch by ensuring DDR stability, power, and performance goals are met.
Bachelor's degree in Engineering, Information Systems, Computer Science or related field with 2+ years of relevant software engineering experience, or Master's with 1+ year, or PhD in relevant disciplines.
2-4 years total work experience in Embedded Systems with strong programming skills in C, Python, C++, or Java.
Relevant work experience in DDR technology including DDR SW driver development, platform driver development, or board bring-up with strong debugging skills on system-level memory issues.
Knowledge of SOC architecture, processor/CPU architecture, RTOS, JTAG, core BSP driver development and debug is mandatory.
Experienced in embedded software development within DDR technology space with demonstrated skills in debugging complex system-level memory issues.
Able to independently own and drive multiple DDR chipsets programs, coordinating with cross-functional teams including hardware and software.
Strong analytical skills to assess data and system test results to identify and resolve DDR stability, power and performance concerns throughout product lifecycle.