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Niche FPGA verification skill lowers competition, but Tier‑1 brand and Bangalore metro increase applicant density.
FPGA/RTL verification skills are highly domain-specific and not easily transferable.
Explicit 7+ years and mandatory SystemVerilog/UVM scripting create high filtering strictness.
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Develop and execute FPGA functional verification plans, test benches, and simulation environments to ensure design meets microarchitecture specifications.
Identify, debug, and resolve issues in pre-silicon FPGA design through system simulation and collaboration with FPGA architects, RTL developers, and physical design teams.
Maintain and improve verification methodologies including gate-level simulation and power-aware simulations, and document verification strategies and test plans.
Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field.
Minimum 7 years of experience in FPGA verification including SystemVerilog and UVM/OVM methodology.
Proficiency in scripting languages like perl or Python.
Location: Bengaluru, Karnataka, India (Shift 1).
Experienced in designing reusable verification components from block level to system level.
Familiarity with multiple RTL simulators, code coverage, functional coverage, and regression testing.
Prior exposure to Ethernet protocol verification and advanced verification techniques such as X-propagation.