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Tier-1 brand and metro role, but niche ASIC verification skills limit applicant pool.
Highly specialized ASIC verification skills reduce transferability across industries.
Explicit 5–8 years plus mandatory SV/UVM/RTL and hardware verification skills make shortlisting highly stringent.
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Lead design verification strategy and testbench development for complex digital ASICs with multiple clock and power domains.
Collaborate closely with multi-site cross-functional teams including Systems, Design, SoC, SW, Validation, and DFT to achieve verification goals and perform integration testing.
Drive project planning, track progress, conduct verification reviews, coverage closure, sign-off and support post-silicon debug activities.
5-8 years experience in digital front end ASIC design verification (System Verilog/UVM, RTL verification) required.
Bachelor's or Master's degree in Electronics, VLSI, Communications, or related engineering field mandatory.
Proficiency in System Verilog, UVM, scripting languages (Perl/Python), and hands-on experience with Cadence and Synopsys verification tools essential.
Experience with verification methodologies including low power verification, clock domain crossing, bus protocols (AHB, AXI), and code/functional coverage analysis required.
Demonstrated ability to lead and mentor junior engineers and manage verification projects across multiple geographies.
Experienced in working at various abstraction levels (Block/Core/IP/Subsystem) with solid system-level integration awareness.
Strong technical expertise in modem/wireless IP verification and formal verification methods is advantageous but not mandatory.