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Tier-1 brand and Bangalore metro increase competition, but niche verification skills moderate applicant density.
Specialized hardware verification protocols and languages limit cross-industry portability.
Explicit protocol, language, and verification methodology requirements plus years make filters strict.
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Develop and maintain UVM-based verification environments for high-speed interconnect protocols such as PCIe, CXL, AXI, and CHI.
Perform block-level and top-level verification including functional coverage, assertion-based verification, and regression testing to ensure design correctness.
Collaborate with RTL designers and architects; debug RTL and gate-level simulation failures; mentor junior engineers and improve verification methodologies.
Bachelor's degree or higher in Computer Science, Electrical/Electronics Engineering, or related field.
3+ years hardware engineering experience with bachelor's, 2+ years with master's, or 1+ year with PhD.
Strong proficiency in System Verilog, UVM, assertion-based verification, and verification methodologies.
Deep knowledge of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and experience with Synopsys/Mentor VIPs.
Experienced ASIC/Subsystem/SoC verification engineer with 6-10+ years preferred, skilled in high-speed protocol verification.
Proficient in scripting languages (Perl, Python, Tcl) and power-aware verification methodologies including UPF and formal verification.
Capable of driving verification closure through coverage convergence and collaborating across design and architecture teams.