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Highly specialized static timing expertise and senior staff level reduces applicant density despite strong brand.
Deep EDA/timing signoff specialization limits transferability across industries.
Mandates PrimeTime, MMMC/OCV/AOCV/POCV signoff expertise and scripting, creating strict technical filters.
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Resolve complex timing closure and signoff challenges for advanced node semiconductor designs directly with leading customers, ensuring tapeout schedules are met.
Debug critical timing issues using Synopsys PrimeTime including setup/hold violations, clock domain crossings, signal integrity and variability effects at 5nm and below nodes.
Collaborate with R&D and product teams to reproduce issues, drive tool and methodology improvements, and deliver automation scripts and technical training to customers.
Bachelor's degree in Electronics and Communication Engineering plus Master's in VLSI, Embedded Systems, or Communication Systems.
Strong hands-on experience with Synopsys PrimeTime static timing analysis and signoff on real production designs.
Deep understanding of timing constraints (SDC), MMMC analysis, and variation-aware methodologies (OCV, AOCV, POCV) for advanced nodes (5nm and below).
Proficiency in Tcl scripting for automation; Python or Perl scripting is a strong plus; Work Experience Required: Not explicitly mentioned in the JD.
Experienced in debugging and resolving advanced timing closure issues independently and under tight tapeout deadlines, capable of prioritizing between R&D escalation and methodology solutions.
Skilled in direct customer engagement, able to translate complex timing analysis into actionable guidance and build trusted technical relationships.
Demonstrated ability to design practical automation scripts and methodology improvements tailored to customer environments at advanced semiconductor process nodes.