Back
Tier-1 employer and Bangalore metro increase competition, but niche formal verification skillset moderates applicant density.
Highly domain-specific semiconductor formal verification skills limit transferability across industries.
Explicit 4–13 years requirement plus mandatory formal verification, SystemVerilog, and proof expertise make filtering strict.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Own end-to-end formal verification of interconnect fabric, protocol bridges, and link-layer logic, including property specification and proof convergence across multiple protocols.
Develop and execute formal verification test and coverage plans, create abstraction models, and generate formal proofs to verify complex designs.
Collaborate with architecture, RTL design, and physical design teams to improve verification and maintain/enhance formal verification tools and methodologies.
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related discipline.
4 to 13 years of hands-on experience in Formal Verification.
Proficiency in formal verification tools and methodologies including model checking and equivalence checking.
Strong knowledge of System Verilog, Verilog, logic/microarchitecture fundamentals, abstraction modeling, and familiarity with BDD and Data Flow Graphs.
Experienced in applying formal verification with strong protocol knowledge and hands-on coding skills in a silicon/chip design environment.
Capable of collaborating across architecture, RTL, and physical design disciplines to solve complex architectural and verification problems.
Demonstrated ability to document, mentor junior engineers, and drive quality and schedule adherence in formal verification projects.