Back
Tier-1 employer in Bangalore and mid-level role increases applicant density despite specialized ASIC skills.
ASIC verification is highly specialized hardware verification work, limiting cross-industry transferability.
Explicit degree, mandatory 3+ years, and specific SystemVerilog/UVM and scripting requirements increase filter rigidity.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Develop and architect block-level and full-chip verification environments for ASICs using SystemVerilog and UVM methodologies.
Independently verify large ASIC blocks, perform code and functional coverage analysis, and sign off for tape-out including gate level simulation.
Collaborate closely with logic designers and software developers to debug issues and support software development and bring-up; automate verification processes using scripting (Perl, Python, shell).
Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) is required.
Minimum 3 years of ASIC verification experience using SystemVerilog.
Experience with verification methodologies like UVM (strong plus) and scripting in Perl and/or Tcl preferred.
Work location: Hybrid role requiring approximately 2 days per week at HPE office; other location constraints not explicitly mentioned.
Experienced ASIC verification engineer skilled in advanced methodologies (UVM) and constrained-random verification.
Able to independently own large ASIC block verification and deliver tape-out ready sign-offs under timelines.
Comfortable working in a cross-functional team involving logic design and software development for networking ASIC products.