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Tier-1 employer, Bangalore metro, and mid-level role increases application competition.
ASIC verification skills are specialist and mainly transferable across semiconductor companies, not general industries.
Explicit 2+ years plus mandatory SystemVerilog/UVM and coverage requirements enforce strict technical filtering.
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Verify design, architecture, and micro-architecture of complex memory subsystem IPs using advanced methodologies.
Develop verification infrastructure including functional models, scoreboards, and verification environments primarily using UVM methodology.
Define verification scope, create testplans, achieve functional coverage closure, and collaborate across teams for timely solutions.
Bachelor's or Master's degree in Electrical Engineering (EE) or Electronics and Communication Engineering (ECE).
2+ years of relevant experience in verification of complex IPs or subsystems.
Expertise in standard verification flows such as SystemVerilog random testing, UVM, formal verification, and coverage driven methodologies.
Strong coding skills in SystemVerilog (SV).
Experience specifically in verification of memory subsystems or network interconnect IPs is a significant advantage.
Knowledge of memory subsystem concepts like cache coherency, memory consistency models, arbitration policies, high-speed IO protocols, and on-chip interconnects.
Familiarity with scripting languages such as Perl or Python to aid in automation and infrastructure development.