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Tier-1 brand, metro Bangalore location, and mid-level (3–6 years) experience increase candidate competition.
High because the role demands specialized RTL/SystemVerilog UVM and ARM protocol verification domain expertise.
High due to explicit 4+ years requirement plus mandatory SystemVerilog/UVM and ARM protocol expertise.
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Own unit-level verification of HSIO IP in automotive chips, focusing on ARM architecture based distributed interconnect fabric.
Develop UVM-based testbenches, define test plans, and implement verification infrastructure at module, cluster, and system levels.
Collaborate with architects, designers, FPGA, and post-silicon teams to ensure unit robustness and lead verification closure.
BTech or MTech in ECE, EE, CSE, or equivalent degree required.
4+ years experience in verification closure of complex units, sub-systems, or SoC level verification.
Proven experience with ARM architecture and protocols (AXI, AHB, APB).
Proficient in SystemVerilog and UVM methodologies for verification.
Experienced in developing reusable verification components like BFMs, monitors, checkers, and scoreboards with a strategic approach to verification environment architecture.
Comfortable driving verification from unit to system level and coordinating closure processes in collaborative matrix teams.
Additional exposure to AI-assisted code development and Formal verification considered strong pluses.