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Tier-1 employer, Bangalore metro, and mid-level role increase applicant density despite niche verification specialization.
Hardware UVM verification skills are highly domain-specific, limiting cross-industry transferability.
Explicit 4+ years and mandatory UVM/tool expertise make filters strict.
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Own creation and architecture of UVM based verification test benches and methodologies for complex IPs and sub-systems in automotive chips.
Define and execute test plans including building bus functional models, monitors, checkers, scoreboards, and implementing functional coverage for verification closure.
Collaborate with architects, designers, FPGA and post-silicon teams to ensure robustness of the verification unit.
BTech/MTech degree required.
Minimum 4+ years of experience in verification closure at Unit, Sub-system or SoC level.
Experience with UVM/VMM verification methodologies and industry standard verification tools for simulation and debug is mandatory.
Experience domains preferred: CPU, Memory Controller, Interconnect, High Speed IO (UFS/PCIe/XUSB), Ethernet MAC/Switch, Bus Protocols (AXI/APB), and system functions like Safety and Security.
Experienced in complex verification environments involving multi-domain IPs and SoC level testing.
Strong analytical and debugging skills with ability to drive verification closure independently.
Effective communicator capable of collaborating across cross-cultural and matrix organizational teams.