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Tier-1 brand plus mid-level requirement but niche AMS verification reduces broad applicant competition.
Highly specialized hardware verification skills (UVM, Verilog-AMS, RNM, DDR/ONFI) limit cross-industry transferability.
Explicit 5+ years and mandatory UVM/SystemVerilog/AMS and protocol experience create strict filtering.
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Develop and maintain scalable, reusable UVM-AMS verification environments integrating SystemVerilog/UVM with mixed-signal simulators for DDR & ONFI PHY IP.
Own complete IP and sub-system verification lifecycle including test plan creation, UVM development, full-chip co-simulation and signoff.
Lead, mentor, and coach junior engineers while collaborating closely with digital and analog design teams.
5+ years of relevant ASIC AMS verification experience.
Proficiency in SystemVerilog, Verilog, UVM environment and testbench creation.
Experience with AMS simulations and modeling analog circuits using Verilog and Verilog-A.
Degree in Electronics (BS/BE or M.S./M.Tech).
Experienced in high-speed DDR/LPDDR JEDEC, NAND ONFI protocols and analog verification blocks (SDLL, DCC, Band gap).
Hands-on experience with RTL debugging, scoreboarding and coverage analysis in mixed-signal verification environments.
Capable of leading verification projects at IP and subsystem level with strong coordination between analog and digital design disciplines.