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Tier-1 brand and Bangalore increase interest, while niche SoC verification skills limit applicant pool.
Highly specialist SoC verification skills limit cross-industry transferability.
Explicit 5–12 years and mandatory SystemVerilog/UVM and SoC verification skills.
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Own functional correctness and quality assurance of SoC designs pre-silicon through simulation, emulation, and advanced verification methods.
Develop and maintain SystemVerilog/UVM testbenches, verification environments, and constrained-random/directed test scenarios for compute die frontend SoC.
Analyze coverage closure, debug RTL and testbench failures, and collaborate with cross-functional teams to continuously improve verification methodologies and automation flows.
5 to 12 years of relevant experience in front-end pre-silicon SoC/subsystem/IP level verification.
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE) or Computer Science.
Strong proficiency in SystemVerilog and UVM for testbench development and verification environment.
Work Location: Bangalore, India; Work Model: Hybrid (on-site and off-site).
Experienced in defining and executing comprehensive verification plans aligned with architecture specifications for complex SoC designs.
Demonstrated ability to perform constrained-random and directed testing with strong debug and root cause analysis skills in pre-silicon environments.
Skilled at leveraging AI tools to enhance verification coding, debugging, and quality sign-off processes in a large-scale semiconductor environment.