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Tier-1 brand, remote option and Bangalore metro increase applicant competition.
Highly specialized SoC verification and UVM/SystemVerilog skills limit cross-industry transferability.
Mandatory 12+ years and UVM/SystemVerilog expertise create stringent shortlisting filters.
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Define and own verification plans, methodologies, and coverage strategies for complex SoC designs including block, subsystem, and full-chip level.
Architect and implement testbench environments from scratch and enhance existing frameworks including UVM-based components like agents, sequences, drivers, monitors, and scoreboards.
Lead end-to-end verification processes including gate-level simulations, regression, coverage closure, debugging, and mentor junior/mid-level engineers.
Bachelor's degree in Electrical Engineering or equivalent practical experience.
12+ years of experience in design verification including verification methodologies such as UVM.
Proficiency with industry-standard simulators, revision control and regression systems.
Experience with SoC architecture, mixed signal designs and good knowledge of analog components like ADC, DAC, PLL, Oscillators, and PI controllers.
Strong experience in architecting and driving full verification lifecycle for complex SoC or power management designs.
Expertise with UVM, SystemVerilog, Verilog, scripting (Perl, Python), and testbench automation.
Proven technical leadership skills including mentoring teams and owning key verification deliverables in a semiconductor product development environment.