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Senior, niche semiconductor methodology role with metro location but specialized skills reduce applicant density.
Highly specialized semiconductor methodology and EDA expertise limits transferability across industries.
Extremely specific 15+ years, PhD/Master's, and mandatory EDA/methodology leadership requirements.
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Lead the development, deployment, and continuous improvement of EDA/CAD methodologies and design processes for AMS, Digital, and RF IP and SoC development.
Define and execute tool flows, recipes, methodologies, and processes to enhance PPA, productivity, quality, reuse, robustness, and reduce time-to-market across multiple product lines.
Collaborate with R&D design functions and EDA vendors to align methodologies, drive adoption, and implement automation, AI-assisted workflows, and next-gen design technologies.
Master's or Ph.D. in Electrical Engineering, Electronics, Computer Engineering or related field.
15+ years of experience in semiconductor design methodologies and processes with exposure to AMS, Digital, and RF domains.
5+ years of experience leading methodology, EDA, CAD, design enablement or related technical teams.
Hands-on expertise in EDA tools (Cadence, Synopsys, Mentor) and scripting (Python, TCL, Perl).
Deep expertise in semiconductor chip design methodologies across Analog/Mixed-Signal, Digital, RF, and DFT domains with hands-on EDA tool and scripting experience.
Proven leadership in managing technical teams and driving methodology strategy and adoption in large R&D organizations.
Ability to integrate cross-functional teams, work with EDA vendors and foundries, and implement advanced techniques like AI/ML for design automation and optimization.