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Tier-1 brand, Bangalore location and mid-level range balanced by niche semiconductor standard-cell QA specialization.
Highly specialized semiconductor QA skills limit cross-industry transferability.
Explicit 4–13 years plus mandatory standard-cell circuit and post-layout QA expertise enforces strict technical filters.
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Own QA methodologies for standard cell libraries including test plan development, regression testing, and post-layout verification.
Enhance performance and efficiency of standard cell circuits including high-performance flip flops, latches, multi-bit flip flops, voltage level shifters, power optimization cells, and clock cells.
Drive innovation in power optimization and clock cell design impacting product quality and energy efficiency.
4 to 13 years of experience in standard cell circuit design and QA for semiconductor standard cell libraries.
Degree requirement: B.Tech/B.E or M.Tech/M.E in a relevant field.
Strong hands-on experience in developing environments, extracting post-layout netlists, and digital circuit simulation.
Good understanding of CMOS device characteristics, design rules, latch-up, electromigration, and statistical/variation analysis.
Experienced in high-performance standard cell circuit design emphasizing power, performance, and area (PPA) optimization.
Capable of independently handling post-layout verification and regression testing processes in semiconductor environments.
Skilled at innovating in power optimization and clock cell design within an advanced R&D setting focused on semiconductor technologies.