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Tier-1 brand and metro location increase competition, but niche SRAM QA skills narrow applicant pool.
Highly specialized semiconductor QA expertise limits transferability across industries.
Explicit 4–14 years plus specialized SRAM, FINFET, PPA, and GDS requirements enforce strict filters.
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Lead and guide a team of engineers to deliver SRAM IP products within specified timelines from specification to GDS and DK delivery.
Develop and execute QA methodologies including test plan development, regression testing, and post-layout verification for standard cell libraries and SRAM designs.
Analyze and improve SRAM circuit designs for robustness, performance, power, and area trade-offs, including review of layouts and robustness reports.
4 to 14 years of relevant work experience in SRAM QA or related semiconductor design quality assurance.
B.Tech/B.E/M.Tech/M.E degree in a relevant engineering discipline.
Strong knowledge of QA methodologies for standard cell libraries, including test plan development and regression testing.
Experience with QA automation tools and proficiency in statistical/variation analysis for design validation.
Experience in custom or compiler SRAM/ROM development with understanding of RC network and FINFET device fundamentals.
Ability to analyze CMOS device characteristics, design rules, failure mechanisms and implement quality assessment and PPA optimization for digital circuit designs.
Experience leading engineering teams and owning full-cycle SRAM IP delivery from specification to final product release.