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Tier-1 brand, metro location, and mid-level range increase applicants, but niche semiconductor QA reduces competition.
Highly domain-specific VLSI and standard-cell QA skills limit cross-industry transferability.
Explicit 4–13 years and mandatory standard-cell circuit QA/design expertise make filters stringent.
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Develop and execute QA methodologies for standard cell libraries including test plans, regression testing, and post-layout verification.
Design and optimize high-performance standard cell circuits such as flip flops, latches, level shifters, power optimization cells, and clock cells.
Contribute to power optimization and variation analysis to improve product performance and energy efficiency.
4 to 13 years of experience in Standard Cell Circuit design and QA.
Bachelor's or Master's degree in Engineering (B.Tech/B.E/M.Tech/M.E).
Strong hands-on experience in QA methodologies for standard cell libraries and post-layout netlist extraction.
Proficient in digital circuit simulation, CMOS device characteristics, and statistical/variation analysis.
Experienced in designing a broad range of standard cell circuits with focus on performance and power optimization.
Capable of developing and executing rigorous QA processes impacting overall semiconductor product quality.
Comfortable working in a cutting-edge semiconductor R&D environment with cross-domain technologies.