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Tier-1 employer, Bangalore location, mid-level experience but niche UVM verification reduces applicant density.
Specialized UVM/SoC verification expertise is highly domain-specific and not easily transferable across industries.
Explicit 5-8 years and mandatory UVM/SoC verification skills create strict shortlisting filters.
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Own complete verification process for key digital blocks in mixed signal SoCs: testbench architecture, development, functional and code coverage closure.
Use UVM and constrained random methodologies to verify at block and SoC level, including integration verification.
Participate in post-silicon activities such as silicon bring-up, evaluation support, and ATE pattern development for production readiness.
Degree in Electronic Engineering or Computer Engineering.
5-8 years of progressive experience in digital design and verification.
Demonstrated experience in UVM-based testbench development from ground up, functional coverage, code coverage, and assertion development.
Experience with scripting languages (Makefile, Python, Perl); familiarity with AHB/AXI/APB protocols is desirable; knowledge of power aware simulations or formal verification is a plus.
Experienced in both IP and SoC level verification with gate level simulation knowledge.
Skilled in collaborating with global product development teams and clear communication of technical issues to engineering leads.
Familiar with digital signal processing concepts and tools like MATLAB or Octave; experience with HW emulation or FPGA prototyping adds advantage.