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Tier-1 brand and metro location increase candidate density, but role is specialized and senior.
Specialized hardware verification skills (UVM, SystemVerilog, IP verification) are highly industry-specific and less transferable.
Explicit 8+ years and mandatory SystemVerilog/UVM/protocol experience make filters strict and technical.
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Lead unit and IP level verification efforts using coverage-driven constraint random methodologies.
Develop and maintain testbenches including stimulus, agent, monitor, and checker components, incorporating C-based reference models.
Apply expertise in standard protocols such as PCIe, CXL, USB, and Ethernet to ensure compliance and performance in verification processes.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years experience; OR Master's degree with 5+ years; OR PhD with 4+ years related experience.
8+ years experience specifically in unit and IP level verification.
Strong skills in System Verilog, UVM, and test planning techniques.
Working knowledge of coverage driven constraint random verification and scripting languages such as Perl and Python.
Experienced hardware engineer specializing in verification of complex SoC or IP blocks with multi-protocol familiarity (PCIe, CXL, USB, Ethernet).
Proficient in advanced verification methodologies including UVM testbench architecture and integration of C-based reference models.
Capable of independently driving verification strategy, testbench development, and coverage closure in a large-scale engineering environment.