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Tier-1 employer plus Bangalore metro increases competition despite role specialization.
Hardware verification expertise is highly domain-specific and not easily transferable across industries.
Explicit 6+ years requirement and mandatory SystemVerilog/UVM/protocol skills create strict filters.
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Own unit and IP level verification activities with a focus on coverage-driven constrained random verification.
Develop and optimize testbenches including stimulus, agents, monitors, and checkers using SystemVerilog and UVM.
Work with standard protocols such as PCIe, CXL, USB, Ethernet, and support verification involving C-based reference models and scripting (Perl, Python).
6+ years of experience in unit and IP level hardware verification.
Proficiency in SystemVerilog, UVM, and test planning.
Knowledge of standard protocols: PCIe, CXL, USB, Ethernet.
Bachelor's degree in CS, Electrical/Electronics Engineering or related field with minimum 3 years experience; or Master's with 2 years; or PhD with 1 year experience.
Experienced verification engineer with deep expertise in coverage-driven random verification methodologies.
Skilled in developing testbenches and using complex verification frameworks incorporating C-based reference models.
Able to work on cutting-edge hardware protocols and collaborate closely with cross-functional hardware design teams.