Back
Niche DV/SystemVerilog skillset and senior profile reduces applicant density despite metro location.
Domain-specific SystemVerilog/UVM and CPU verification skills limit cross-industry transferability.
Explicit 7-12 years plus mandatory SystemVerilog/UVM, CPU, and interface skills make filters stringent.
Login to See Your Match Score
Create a free account or log in to unlock your CV match score across:
Develop and implement System Verilog/UVM test cases for high performance RISCV CPU verification.
Use internal test generators and tools to target specific coverage and test plan scenarios.
Integrate and work with third party VIPs (e.g. bus VIPs) and interfaces like AXI or PCIE for test development.
7-12 years of Design Verification (DV) experience, preferably in CPU verification.
Proficiency in System Verilog and UVM methodology with strong object-oriented programming skills.
Knowledge of CPU architectures (x86, ARM, or RISC-V) with experience in test writing and test plan implementation.
Right to work in India with successful background and reference checks.
Experienced in CPU verification within data-intensive or high-performance compute environments.
Operates with strong technical expertise in System Verilog, UVM, scripting (preferably Python), and bus interfaces like AXI or PCIE.
Capable of independently developing comprehensive test plans and leveraging test generators to ensure thorough coverage.