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Tier-1 employer, mid-level experience requirement, and Bangalore metro increase applicant competition.
Highly domain-specific semiconductor verification skills reduce cross-industry transferability.
Explicit 2+ years minimum plus mandatory SV/UVM and mixed-signal verification skills.
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Own verification strategy and execution for complex digital mixed signal integrated products, including creation of analog/mixed-signal behavioral models and chip-top verification environments.
Develop verification plans, environments, and self-checking test cases using industry standard SV/UVM methodologies with metric-driven approaches.
Collaborate cross-functionally with design, testing, CAD, and system teams globally to support first-pass silicon success and post-silicon validation while driving time-to-market improvements.
B.Tech or M.Tech degree.
Minimum 2+ years of industry experience in analog/mixed-signal behavioral modeling and full chip verification using digital RTL/PA/Gates.
Good understanding of analog design concepts and mixed signal architectures including Power Management, ADCs, DACs, PLL, band gap references, oscillators, SerDes, and related digital control/signal processing.
Experience in developing verification environments and executing verification/debug of complex mixed signal products at block and chip-top levels using SV/UVM methodologies.
Experienced in defining and deploying verification strategies for large integrated digital mixed signal products with metric-driven verification approaches.
Comfortable working across multiple disciplines and locations collaborating in multifunctional global teams for silicon bring-up and validation.
Proficient in verification tools and scripting languages (e.g., Cadence Virtuoso, Xcelium, Synopsys VCS, Python, Perl, Shell) with knowledge of analog/mixed-signal modeling and digital simulation/debug workflows.